Advancing SiC Substrate Strategy: TSMC Scales Thermal Performance for AI and 3D Packaging
As AI and 3D chip architectures intensify thermal-management challenges, TSMC is centering its next-generation high-thermal-efficiency packaging platform around 12-inch SiC substrates, redefining the competitive landscape of semiconductor heat dissipation and high-performance computing…
Silicon carbide (SiC) is best known as a wide-bandgap (WBG) material that powers highly efficient power electronics and accelerates the global green-energy transition. Yet its potential reaches far beyond power devices. As AI computing and 3D chip architectures push thermal-management demand sharply higher, SiC—with its outstanding thermal and mechanical properties—is opening a new wave of innovation in advanced packaging.
Why 12-inch SiC?
As AI accelerators and 2.5D/3D chip-stack densities continue to climb, heat dissipation has become the dominant limiter of system performance. TSMC, the world’s leading foundry, is actively developing 12-inch single-crystal SiC substrates whose thermal conductivity can reach about 500 W·m⁻¹·K⁻¹—far exceeding traditional ceramic materials such as alumina (Al2O3) and sapphire.
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The initiative, undertaken by TSMC together with partners and equipment suppliers, aims to replace existing ceramic substrates with SiC across a wide range of applications—from augmented-reality (AR) smart lenses to hyperscale data-center processors. In wearable AR lenses, for example, densely packed electronics must operate in tightly enclosed micro-spaces, where thermal control directly affects user safety and device reliability.
TSMC’s decision to exit gallium-nitride (GaN) and focus on new SiC applications reflects both competitive pressure and a rebalancing of its materials strategy. Leveraging SiC’s outstanding thermo-mechanical properties, TSMC is building a scalable, next-generation packaging platform.
Defect-density challenge for 12-inch SiC thermal substrates
While 12-inch SiC substrates for thermal management don’t require the ultra-low defect densities of power devices (MOSFETs, diodes, etc.), crystal integrity remains key to quality.
Structural defects such as micropipes, voids, and dislocations disrupt heat-flow paths, weaken mechanical strength, and impair surface flatness during grinding and CMP. As wafer diameter grows, warpage and deformation become more pronounced, directly affecting die-bond quality and advanced-packaging yield.
Because thermal transport in SiC relies on quantized lattice vibrations, any crystal defect that scatters or impedes phonons—micropipes, voids, dislocations—reduces thermal conductivity and creates local hotspots. The development emphasis therefore shifts from “eliminating electrically active defects” to “ensuring uniform bulk density, very low porosity, and excellent surface flatness”—the keys to high-yield, stable mass production of SiC thermal substrates.
Leveraging SiC’s thermal advantages
SiC combines high thermal conductivity, robust mechanical structure, excellent thermal-stress resistance, and chemical stability, making it ideal for handling the high heat fluxes in 2.5D and 3D chip designs.
In 2.5D integration, dies sit side-by-side on a silicon or organic interposer for short, fast, and power-efficient signal links. In 3D integration, dies are stacked vertically with very high interconnect density via TSVs or hybrid bonding.
Beyond passive cooling, SiC can also enable hybrid cooling schemes—pairing conventional substrates with high-conductivity materials such as diamond or liquid metals—to dramatically improve overall thermal management.
Materials-strategy pivot: from GaN to a renewed focus on SiC
TSMC plans to fully exit the GaN market by 2027 and refocus resources on SiC. Scaling to 12-inch wafers can bring cost benefits and improve process uniformity (fewer process-induced defects per unit area). Even so, crystal defect density, slicing, planarization, and wafer flatness remain core challenges for SiC manufacturing.
For a long time, SiC was virtually synonymous with power devices; now it is crossing into a new field where thermal management is the key bottleneck. TSMC is actively evaluating:
．Conductive N-type SiC as a high-thermal-conductivity substrate;
．Semi-insulating SiC as a potential interposer in chiplet-based architectures.
These directions could reshape the thermal-design architecture of AI accelerators and data-center chips, laying new foundations for future computing platforms.
Thermal management as a competitive edge: SiC breaks packaging thermal limits
In advanced semiconductor design, effective heat dissipation has become a critical differentiator. High-purity diamond reaches ~1,000–2,200 W·m⁻¹·K⁻¹, and single-layer graphene can hit 3,000–5,000 W·m⁻¹·K⁻¹—but both are costly, process-complex, and hard to scale.
Other alternatives—liquid metals, conductive adhesives, and microfluidic cooling—are promising but face cost, manufacturability, and integration trade-offs.
By contrast, SiC offers a pragmatic, balanced solution: strong thermal performance, robust mechanical strength, and scalable high-volume manufacturing—an ideal blend of performance and cost.
TSMC’s technological advantages and global positioning
TSMC’s deep experience in 12-inch wafer manufacturing, combined with its solid production base, rigorous process control, and packaging expertise, allows it to fold SiC into an end-to-end platform strategy—not merely a materials upgrade. This lets TSMC rapidly commercialize AI and HPC chips without restructuring its manufacturing system, cementing its lead in the global semiconductor supply chain.
TSMC’s SiC roadmap is evolving in parallel with paths like Intel’s Backside Power Delivery (BPD) and thermal-power co-design—signaling an industry shift in which thermal management is no longer a supporting function but a core of semiconductor innovation.
TSMC is not just improving heat dissipation; it is building a differentiated packaging platform for AI and HPC, making SiC a cornerstone of the future chip-packaging ecosystem.
Source:TSMC’s SiC Substrate Strategy: Scaling Thermal Performance for AI and 3D Packaging, by Filippo Di Giovanni; translated by Susan Hong.
Also published in EE Times Asia, November–December 2025 issue.